Sample Rate: 1.8 ms (differential) or 3.6 ms (single-ended) for all channels
Special Versions: 60 Hz rejection (T3420A) and fast response (T3420AF)
Electrical Isolation: 2500 V isolation between analog and digital circuits
Front Panel Indicators: Individual LEDs for module active and fault status
Certification: TÜV certified for safety, Risk Class 5
Operation Workflow
1
Signal Conditioning & Conversion
Analog field signals are conditioned and multiplexed into an analog-to-digital converter. Signals are converted into 12-bit digital data stored in the module's RAM. Digital logic circuits are optically isolated from analog signals for protection against field transients and overvoltages.
2
Data Requests from Processor Modules
Processor modules send triplicated read data requests over the I/O Safetybus. The module votes the processors' addressing and data requests, preventing upstream I/O Safetybus failures from affecting module operation. The voted result is passed to the I/O bus interface logic.
3
Retrieving Analog Data
Upon receiving the voted read request, the I/O bus interface logic retrieves analog data values from RAM. Data is placed into three independently powered bus drivers, preventing single driver failures from affecting other I/O busses.
4
Data Transmission to Processors
Bus drivers transmit data via the backplane I/O Safetybus to I/O transceiver modules, which forward data to processors.
5
Data Packaging
12-bit analog input data is packaged as a 16-bit integer: least significant 12 bits represent the analog value (0-4095), with two remaining bits used to flag alarms.
Testing & Diagnostics
1
Voter Circuit Testing
Processor modules periodically test each module's voter circuits by sending discrepant data through one I/O Safetybus leg. Failure to return correct majority-voted result triggers I/O module error indication at processors and module fault indication at I/O module.
2
Module Identification
Each module type has a unique identification code read by the controller, enabling proper module type detection and addressing. Removal or replacement with different types generates I/O module errors.
3
Loopback Logic Testing
Periodic write-and-read-back operations verify proper functioning of the module's I/O bus interface logic.
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